sw/cpld_test/cpld_test.vhd


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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity cpld_test is
	IN_PIN: in std_logic;
	OUT_PIN: out std_logic;
end;

architecture behavioral of cpld_test is
begin
	OUT_PIN <= not(IN_PIN);
end behavioral;