TyposHEADmaster

3 files changed, 5 insertions, 3 deletions

diff --git a/tex/samples.tex b/tex/samples.tex
index 0e335d2..c272e05 100644
--- a/tex/samples.tex
+++ b/tex/samples.tex
@@ -32,7 +32,7 @@ end entity `\reqph{name}`_tb;
 architecture tb of `\reqph{name}`_tb is
   -- simulator settings
   constant freq : natural := `\reqph{frequency}`;
-  constant time : time := 1 sec / freq;
+  constant T    : time := 1 sec / freq;
 
   -- component of DUT
   component `\reqph{name}` is
diff --git a/tex/testbench.tex b/tex/testbench.tex
index 71496f2..dc52453 100644
--- a/tex/testbench.tex
+++ b/tex/testbench.tex
@@ -3,6 +3,8 @@ To simulate a digial circuit it is possible to write test benches using VHDL.
 The code in this section may no longer be synthetisable, and is usually
 written by a \emph{test designer}.
 
+%% TODO: Talk about DUT, with an image?
+
 \subsection{Simulator}
 VHDL simulates digital systems using \emph{delta cycles}.
 
@@ -106,7 +108,7 @@ Assertions are used write tests to check that a signal is in the correct state.
 \end{lstlisting}
 The \vhdl{report} and \vhdl{severity} are optional but strongly advised. The
 severity can take one of 4 values: \vhdl{note}, \vhdl{warning}, \vhdl{error},
-\vhdl{failure}. Simulations can be configured to stop in when an error of the
+\vhdl{failure}. Simulations can be configured to stop when an error of the
 desired severity occurrs. An example:
 \begin{lstlisting}[language=vhdl]
 assert (tb_y = '0') report "error at vector 11" severity error;
diff --git a/tex/vhdl.tex b/tex/vhdl.tex
index 06dabd0..38afe24 100644
--- a/tex/vhdl.tex
+++ b/tex/vhdl.tex
@@ -664,7 +664,7 @@ generic(
   `\reqph{param name}` : `\reqph{type}` := `\reqph{initial value}`
 );
 \end{lstlisting}
-that has affects at \emph{synthesization time}.
+that has effect at \emph{synthesization time}.
 
 \subsubsection{Generic entity and declaration}
 Entities are parametrized as follows.