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authorNao Pross <naopross@thearcway.org>2017-05-19 16:14:00 +0200
committerNao Pross <naopross@thearcway.org>2017-05-19 16:14:00 +0200
commitf2418d7f5a9734590c4e0d3392886423b2e818a9 (patch)
tree8b1c928cee9f975b81b77135174610161e0120ab /hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 11-16-39.LOG
parentwiring for 7 segment displays and traces for the remaining CPU signals (diff)
downloadz80uPC-f2418d7f5a9734590c4e0d3392886423b2e818a9.tar.gz
z80uPC-f2418d7f5a9734590c4e0d3392886423b2e818a9.zip
finish wiring and add eurocard compliant standard holes
since there wasn't enough space (I should have added the holes before beginning) there are only 4 holes instead of 6 (2 will be cut out since the space is unused).
Diffstat (limited to 'hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 11-16-39.LOG')
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diff --git a/hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 11-16-39.LOG b/hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 11-16-39.LOG
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+Added Component: Designator=J2(KLD-0202)
+Added Pin To Net: NetName=NetC11_2 Pin=J2-1
+Added Pin To Net: NetName=NetC11_2 Pin=J2-1
+Added Pin To Net: NetName=DB9-5 Pin=J2-2
+Added Pin To Net: NetName=DB9-5 Pin=J2-2
+Added Pin To Net: NetName=NetJ2_3 Pin=J2-3
+Added Pin To Net: NetName=NetJ2_3 Pin=J2-3
+Added Member To Class: ClassName=Peripherals Member=Component J2 PWR2.5