diff options
| author | Nao Pross <naopross@thearcway.org> | 2018-10-30 11:41:24 +0100 |
|---|---|---|
| committer | Nao Pross <naopross@thearcway.org> | 2018-10-30 11:41:24 +0100 |
| commit | 43be150dc6e84f6f6eeb071cd3cdb7fc21125d60 (patch) | |
| tree | 541fd3d690c1bdfd7b68d684029a400b80f4aa06 /sw-old/cpld/address_decoder.mod | |
| parent | Add datasheets for ATmega328 and 74LS259 (diff) | |
| download | z80uPC-43be150dc6e84f6f6eeb071cd3cdb7fc21125d60.tar.gz z80uPC-43be150dc6e84f6f6eeb071cd3cdb7fc21125d60.zip | |
Move sw to sw-old and hw to hw-altium, add kicad files
Diffstat (limited to 'sw-old/cpld/address_decoder.mod')
| -rwxr-xr-x | sw-old/cpld/address_decoder.mod | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/sw-old/cpld/address_decoder.mod b/sw-old/cpld/address_decoder.mod new file mode 100755 index 0000000..8724fa0 --- /dev/null +++ b/sw-old/cpld/address_decoder.mod @@ -0,0 +1,58 @@ +MODEL
+MODEL_VERSION "1.0";
+DESIGN "address_decoder";
+DATE "Mon Nov 13 11:47:14 2017";
+VENDOR "Lattice Semiconductor Co. Ltd.";
+PROGRAM "STAMP Model Generator";
+
+/* port name and type */
+INPUT MMU_IN_2;
+INPUT MMU_IN_3;
+INPUT MMU_IN_4;
+INPUT MMU_IN_5;
+INPUT MMU_IN_6;
+INPUT MMU_IN_7;
+INPUT MMU_IN_8;
+INPUT MMU_IN_9;
+INPUT MMU_IN_10;
+INPUT MMU_IN_11;
+INPUT MMU_IN_12;
+INPUT MMU_IN_13;
+INPUT MMU_IN_14;
+INPUT MMU_IN_15;
+OUTPUT CSCTC;
+OUTPUT CSPIO;
+OUTPUT CSRAM;
+OUTPUT CSROMH;
+OUTPUT CSROML;
+OUTPUT CSUART;
+OUTPUT MMU_OUT_12;
+OUTPUT MMU_OUT_13;
+OUTPUT MMU_OUT_14;
+OUTPUT MMU_OUT_15;
+
+/* timing arc definitions */
+MMU_IN_2_CSUART_delay: DELAY MMU_IN_2 CSUART;
+MMU_IN_3_CSUART_delay: DELAY MMU_IN_3 CSUART;
+MMU_IN_4_CSUART_delay: DELAY MMU_IN_4 CSUART;
+MMU_IN_5_CSUART_delay: DELAY MMU_IN_5 CSUART;
+MMU_IN_6_CSUART_delay: DELAY MMU_IN_6 CSUART;
+MMU_IN_7_CSUART_delay: DELAY MMU_IN_7 CSUART;
+MMU_IN_8_CSCTC_delay: DELAY MMU_IN_8 CSCTC;
+MMU_IN_8_CSPIO_delay: DELAY MMU_IN_8 CSPIO;
+MMU_IN_8_CSUART_delay: DELAY MMU_IN_8 CSUART;
+MMU_IN_9_CSCTC_delay: DELAY MMU_IN_9 CSCTC;
+MMU_IN_9_CSPIO_delay: DELAY MMU_IN_9 CSPIO;
+MMU_IN_9_CSUART_delay: DELAY MMU_IN_9 CSUART;
+MMU_IN_10_CSCTC_delay: DELAY MMU_IN_10 CSCTC;
+MMU_IN_10_CSPIO_delay: DELAY MMU_IN_10 CSPIO;
+MMU_IN_10_CSUART_delay: DELAY MMU_IN_10 CSUART;
+MMU_IN_11_CSCTC_delay: DELAY MMU_IN_11 CSCTC;
+MMU_IN_11_CSPIO_delay: DELAY MMU_IN_11 CSPIO;
+MMU_IN_11_CSUART_delay: DELAY MMU_IN_11 CSUART;
+MMU_IN_12_CSCTC_delay: DELAY MMU_IN_12 CSCTC;
+MMU_IN_12_CSPIO_delay: DELAY MMU_IN_12 CSPIO;
+
+/* timing check arc definitions */
+
+ENDMODEL
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