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author | Nao Pross <naopross@thearcway.org> | 2017-06-16 15:25:54 +0200 |
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committer | Nao Pross <naopross@thearcway.org> | 2017-06-16 15:25:54 +0200 |
commit | 6105426e159a55cfb15fee3e999bb4fcf6289446 (patch) | |
tree | 658b62ff706fcd81674901bc4bfd4dbb9667ebdd /sw/cpld_test/cpld_test.prj | |
parent | fixed typo in usart.h and in doc (diff) | |
download | z80uPC-6105426e159a55cfb15fee3e999bb4fcf6289446.tar.gz z80uPC-6105426e159a55cfb15fee3e999bb4fcf6289446.zip |
new components list and cpld test unit
Diffstat (limited to 'sw/cpld_test/cpld_test.prj')
-rw-r--r-- | sw/cpld_test/cpld_test.prj | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/sw/cpld_test/cpld_test.prj b/sw/cpld_test/cpld_test.prj new file mode 100644 index 0000000..eb5548a --- /dev/null +++ b/sw/cpld_test/cpld_test.prj @@ -0,0 +1,34 @@ +#-- Lattice Semiconductor Corporation Ltd. +#-- Synplify OEM project file //nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test\cpld_test.prj +#-- Written on Thu Jun 01 13:51:28 2017 + + +#device options +set_option -technology mach +set_option -part M4A5-32 + +#compilation/mapping options + +#map options + +#simulation options +set_option -write_verilog false +set_option -write_vhdl false + +#timing analysis options +set_option -synthesis_onoff_pragma false + +#-- add_file options +add_file -vhdl -lib work "cpld_test.vhd" + +#-- top module name +set_option -top_module cpld_test + +#-- set result format/file last +project -result_file "cpld_test.edi" + +#-- error message log file +project -log_file cpld_test.srf + +#-- run Synplify with 'arrange VHDL file' +project -run |